Author Topic: CRC error detection  (Read 855 times)


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CRC error detection
« on: November 16, 2015, 10:20:45 AM »
CRC error detection provides real-time error detection on the DDR4 data bus, improving
system reliability during WRITE operations. DDR4 uses an 8-bit CRC header error
control: X8+X2+X+1 (ATM-8 HEC).
High-level, CRC functions:
• DRAM generates checksum per write burst, per DQS lane
– 8 bits per write burst (CR0–CR7)
– CRC using 72 bits of data (unallocated transfer bits are 1s)
• DRAM compares against controller checksum; if two checksums do not match,
DRAM flags an error, as shown in Figure 2
• A CRC error sets a flag using the ALERT_n signal (short low pulse; 6–10 clocks)
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Re: CRC error detection
« Reply #1 on: June 24, 2016, 10:26:34 AM »
A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short check value attached, based on the remainder of a polynomial division of their contents.